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scalable AI. What we call “CMOS 2.0” captures
the shift toward a coordinated approach across the
stack: moving from a single CMOS scaling roadmap
to a richer design space of stacked logic layers,
heterogeneous devices, advanced interconnects and
ever-tighter compute-memory integration.
That richer design space also creates new and
complicated optimization challenges. Power, thermal
behavior, memory, packaging, software and reliability are becoming highly interdependent. This
requires what we call cross-technology co-optimization (XTCO), a methodology for co-optimizing
across technologies and physics as early in the
design process as possible, so that improving one
layer doesn’t weaken the system as a whole.
Orchestration as a competitive advantage
No single company can solve this puzzle alone. The
bottlenecks now cut across foundries, fabless companies,
IDMs, equipment suppliers, EDA vendors, hyperscalers,
disruptive startups, universities and research organizations. Ecosystem orchestration is therefore no longer a
support function; it has become one of the semiconductor
industry’s defining sources of competitive advantage. In
practice, technology and ecosystem orchestration means
shared roadmaps, early validation, test vehicles for XTCO
and a shorter loop between research, design and manufacturing, ultimately bridging the gap from lab to fab.
In the AI era, the semiconductor ecosystem can no longer
solve scalability alone, at least not in the form in which it
has traditionally operated. That ecosystem has excelled at
bringing together deep expertise across materials, devices,
equipment, process technology and manufacturing to enable
breakthroughs in manufacturability. But AI now forces a
broader, more holistic optimization challenge: performance,
energy efficiency and scalability have to be addressed
across compute, memory, interconnects, packaging,
software, algorithms and infrastructure. The collaboration
model itself must expand, bringing foundries, IDMs,
equipment suppliers and research organizations together
with fabless companies, algorithm labs, hyperscalers and
emerging neocloud players.
Ultimately, the winners of the AI race will be those
that can extend the semiconductor industry’s proven
model of ecosystem collaboration beyond manufacturability, connecting fabs, fabless innovators, algorithm
labs and neoclouds into one coordinated effort to scale
compute sustainably.
Has AI Shifted the Sustainability Balance from
Chip Design to Manufacturing?
JOHN BLYLER, S e n i o r C o n t r i b u t i n g E d i t o r , S e m i c o n d u c t o r D i g e s t
Efficient chip design still matters, but the AI build-out is moving the
sustainability burden onto the fabs.
For decades, semiconductor sustainability was largely a chip design
problem: better performance per
watt, specialized ASIC accelerators,
www.semiconductordigest.com
smarter power management and
architectural improvements. With the
rise of AI and the massive build-out
of new fabs, the equation has
changed. Sustainability now requires
co-optimization across design (materials, devices and systems), the fab
and the AI factory. Continued on page 18
Thursday, October 15 | 17
